1. Technical Field of the Invention
The present invention relates to the field of integrated circuit, and more particularly to diode-based semiconductor memory.
2. Prior Arts
With a simple structure, diode-based memory has a low manufacturing cost and high storage density. There are many types of diode-based memory. One is planar diode-based memory (referring to de Graaf et al. “A Novel High-Density Low-Cost Diode Programmable Read Only Memory”, Technical Digest of the International Electron Device Meeting, 1996). As illustrated in FIG. 1, its chip comprises two areas: a memory array 10 and a peripheral circuit 20. The memory array 10 comprises a plurality of N+ word lines 18, P+ bit lines 12, and memory cells 17. Each memory cell 17 comprises an antifuse 16 and a diode. The diode is comprised of a P+ layer 12, a P− layer 14, and an N+ layer 18. The antifuse 16 is comprised of a thin dielectric, which has a high resistance when unprogrammed and a low resistance when programmed. The peripheral circuit 20, including drivers and sense-amplifiers, provides cell selection/programming/read function for the memory array 10. Its major building block are transistors 27, which further comprise gate 28 and source/drain 24.
In the planar diode-based memory, diodes 17 are located in the same plane (i.e. in the substrate 00) as transistors 27. Although diode itself requires a small mask count (in this case, seven), inclusion of transistors in the same plane leads to a higher mask count (in this case, eleven) and therefore, a relatively high manufacturing cost.
Another type of the diode-based memory is three-dimensional electrically-programmable memory (3D-EPM, referring to U.S. Pat. No. 5,835,396, “Three-Dimensional Read-Only Memory” issued to Zhang, U.S. Pat. No. 6,034,882, “Vertically Stacked Field Programmable Nonvolatile Memory and Method of Fabrication”, issued to Johnson et al. and others). Among various three-dimensional memories (3D-M), 3D-EPM was considered having the greatest potential for commercialization in the past. As illustrated in FIG. 2, a 3D-EPM comprises at least two levels: a substrate level 30 and an electrically-programmable memory level 40. The memory level 40 comprises a plurality of world lines 42, bit lines 48 and memory cells 47. Each memory cell 47 comprises an antifuse 46 and a diode. The substrate level 30 comprises a plurality of transistors 37, which further comprise gate 38 and source/drain 34.
A major challenge faced by 3D-EPM is its scalability. Because the antifuse programming current does not scale with technology, its programming-current density increases in proportional to the square of the scaling factor. As 3D-EPM is scaled to more advanced technology, this programming-current density becomes too large to be tolerated by the connecting diode (at the 0.2 μm node, the programming-current density has reached ˜104 A/cm2). It is anticipated that 3D-EPM will have difficulty to scale to the 50 nm node. This, in turn, will greatly limit its storage density.
In sum, the prior-art diode-based memory has either a relatively high manufacturing cost, or a limited storage density. To overcome these shortcomings, the present invention discloses a small-pitch three-dimensional mask-programmable memory (SP-3DmM). SP-3DmM is an ultra-low-cost and ultra-high-density semiconductor memory.